About Synopsys :
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
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Synopsys Recruitment 2022
|Post Name||Intern (Technical-Engineering)|
|Salary||₹6 – 8 LPA|
- The focus of work would be RTL design & Formal Verification in one of the following areas related to connectivity protocols:
- USB/Ethernet/AMBA/MIPI/Memory Controllers
- Architecture exploration of the sub-blocks within one of these IPs to optimize for the area, speed, and power
- VLSI Design & Formal Verification of these sub-blocks/exploration of latest features and standards.
- Based on the project assigned, the job would involve one or more of the following activities: Verilog/System Verilog/ Vera coding, Exposure to UVM methodology, working with EDA tools like Design Compiler for Synthesis, SpyGlass for Lint, VCS for simulation.
- The candidate must have completed Bachelor’s degree in Electronics/ Electrical Engineering.
- Partial completion of MS/MTech is preferable (Electrical/Electronics/VLSI/MicroElectronics or allied specializations.)
- Minimum 7.0 CGPA/ 70% in Bachelor’s in Engineering and 7.5 CGPA in Masters till the current semester.
- Need to be backed with consistently high academics in the 10th std and 12th standard.
- Sound fundamentals in Digital electronics.
- HDL Languages coding experience preferably in Verilog/Vera/System Verilog.
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